This invention relates to a logical waveform generator which generates a logical waveform having its phase and pulse width varied on the basis of a clock signal.
The waveform generator of this kind is employed to produce a test waveform for testing a logical circuit fabricated as a semiconductor integrated circuit, for example. This is, in order to test such a logical circuit as to whether or not it performs a normal operation when simultaneously supplied at its plurality of terminals with various data, it is determined to what extent the timing of the data can be deviated and how much the widths of the data can be reduced while the circuit operates normally. For such a test, it is necessary to prepare data of various phases (timings) and widths based on a clock signal, and to apply the data to the logical circuit under test.
When the logical circuit is supplied with logical data, a certain time period is required for the logical circuit to perform the operation corresponding to the input data. This period is called a set-up time Ts. Further, an incorrect output is produced from the logical circuit unless the data is held for a certain minimum period of time called a hold-off time Th. Because of the set-up time Ts and the hold-off time Th, required in conventional logical waveform generators, a clock signal for changing the timing of data cannot be set at a desired moment throughout one time slot Tc but can be set only at a desired moment in a period Tc-(Ts+Th). Accordingly, it is impossible to obtain a desired logical waveform and to sufficiently check the logical circuit under test. Moreover, since the phase of the clock signal can be set only in the period Tc-(Ts+Th) as mentioned above, it happens that in the case of high-speed logical data, the time slot Tc is reduced, and various waveforms for testing the logical circuit essentially cannot be produced. In addition, the conventional logical waveform generators cannot generate a waveform extending over a plurality of time slots.